1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the semiconductor device, and more particularly to a semiconductor device having silicon on insulator (SOI) and a fabricating method therefor, by which a distance between a diode and a well resistor of the SOI semiconductor device is shortened to achieve high integration without degradation in insulating characteristics in the device.
2. Description of the Prior Art
Recently, great attention has been drawn to the SOI technique, in which a monocrystalline silicon layer is formed on an insulating layer to integrate semiconductor unit elements. If the SOI technique is applied to fabricating a semiconductor device, it can reduce junction capacitance in driving the semiconductor device, so as to improve its operational speed compared with a general bulk semiconductor device.
However, due to a structural characteristic of the SOI semiconductor device, a silicon substrate and a unit device formed thereon are completely separated by an insulating layer, commonly referred to as a buried oxide (BOX) layer. As a result, a unit element like a diode is typically formed as a lateral element for integrating electronic circuits on the SOI substrate, causing a limitation in use of a well structured element such as a resistor for integrated circuits. As a result, the diode has not been made in the vertical NPN (or PNP) structure commonly used for an electro static discharge (ESD) circuit or the like, causing difficulty in fabricating an integrated circuit.
If a vertical NPN (or PNP) diode is replaced by lateral NPN (or PNP) diode, the driving capacity is reduced to approximately half. Therefore, it is necessary to fabricate the unit element (diode) of the vertical NPN structure twice as large as that of the horizontal NPN structure to compensate for this disadvantage. Accordingly, the area is also proportionally required for fabricating a larger unit element, resulting in a negative effect on the integration level of the highly integrated circuit.
Therefore, in order to allow such a unit element to be fabricated in the same structure within the same area as used for a conventional semiconductor device, the SOI semiconductor device is fabricated by selectively etching a predetermined portion of the upper silicon layer and BOX layer, and forming the unit elements inside a lower silicon layer.
FIG. 1 is a cross-sectional view illustrating a conventional structure of a SOI semiconductor device fabricated according to the aforementioned method. The conventional structure of FIG. 1 includes a semiconductor device having a diode.
According to the cross-sectional view in FIG. 1, the conventional SOI device includes a SOI substrate having a surface silicon layer 10c formed by inserting an insulating layer 10b on a P type semiconductor substrate 10a. An element separating layer 12 is formed at a predetermined portion (an element separating region) of the surface silicon layer 10c for enabling its bottom surface to contact the insulating layer 10b. A gate electrode 16 is formed by inserting a gate insulating layer 14 at a predetermined portion of the surface silicon layer 10c. An insulating spacer 20 is formed at both side walls of the gate electrode. A source/drain region 22 is formed in the surface silicon layer 10c at both edges of the gate electrode 16 for enabling its bottom part to contact the insulating layer 10b. A first groove (g1) formed at one side of the gate electrode 16 for penetrating the surface silicon layer 10c and insulating layer 10b to expose a predetermined portion of an active region of a N well 24 formed inside the semiconductor substrate 10a. A P type first diffusion region 26 is formed inside the N well 24 at the bottom of the first groove (g1). A second groove (g2) is formed at one side of the first diffusion region 26 by penetrating the surface silicon layer 10c and insulating layer 10b to expose a predetermined portion of the active region of the silicon substrate 10. A N+ type second diffusion region 28 is formed in the silicon substrate 10a under the second groove (g2). An interlevel insulating layer 30 having a plurality of contact holes (h) is formed on the resultant structure to expose a predetermined portion of the surface of the first and second diffusion regions 26, 28. Metal wires 32 are formed for separately connecting the first and second diffusion regions 26, 28. Item 18 is a silicide layer formed for reducing voltage levels of the gate electrode and contact wires.
Accordingly, in case of the SOI device thus constructed, a surface silicon layer 10c surrounded by insulating layer 10b and device separating layer 12 is used for a transistor channel region, the first diffusion region 26 and N well 24 for P+/N diode, and the second diffusion region 28 and P type silicon substrate 10a for N+/P diode.
However, there are several drawbacks to the SOI device thus constructed. The distance I between the N well 24 formed for the P+/N diode and the second diffusion region 28 formed for the N+IP diode is reduced enough to allow the N well 24 and the second diffusion region 28 to meet each other in the silicon substrate 10a. At this time, the silicon substrate 10a does not have a function for separation to thereby reduce the operational property of the semiconductor device. Therefore, it is very important to secure a sufficient distance between those diodes of the SOI semiconductor device constructed in the structure shown in FIG. 1. Therefore, there are problems in the conventional method for fabricating the SOI semiconductor device in that there is given a limitation in shortening the distance between diodes for fabricating a highly integrated semiconductor device according to designing rules.
Therefore, it is an object of the present invention to solve the aforementioned problems and provide a SOI semiconductor device by modifying its structure of separating P+/N diode from N+/P diode with STI at the semiconductor substrate in the process of designing the SOI device, so that, however short the distance between diodes may be, an actual distance between those diodes in the silicon substrate, that is, an effective distance for separation, is large enough to make no difference in the insulating property and achieve the same operational level of the integrated circuit as the conventional SOI device, even if the SOI device is fabricated in an area smaller than that required for the conventional SOI device.
It is another object of the present invention to provide a method for effectively fabricating a SOI semiconductor device of the present invention.
In order to accomplish the aforementioned objects of the present invention, there is provided a SOI semiconductor device of the present invention which includes a semiconductor substrate of a first conductivity type. A surface silicon layer is formed by inserting an insulating layer on the semiconductor substrate. A trench is formed by etching a predetermined portion of surface silicon layer, insulating layer and substrate to expose a part of the semiconductor substrate to be used for an element separating region, and a STI is formed in the trench. A transistor is constructed on the surface silicon layer surrounded by the insulating layer and STI with a gate electrode being positioned at the center thereof and with a source/drain region being formed in the surface silicon layer of both edges of the gate electrode for enabling its bottom part to be in contact with the insulating layer. A first groove is formed between the STI at one side of the transistor by etching the surface silicon layer and insulating layer to expose a predetermined portion: of an active region of a second-conductivity-type well in the semiconductor substrate. A second groove is formed between the STI at one side of the first groove by etching the surface silicon layer and insulating layer to expose a predetermined portion of the active region of the semiconductor substrate. A first diode diffusion region of the first conductivity type is formed in a second-conductivity-type well under the first groove. A second diode diffusion region of a second conductivity type is formed in the semiconductor substrate under the second groove.
In one embodiment, the device can include another first-conductivity-type well in the semiconductor substrate under the second groove to allow the second diode diffusion region to form in the second first-conductivity-type well. The device can also be constructed with a first-conductivity-type impurity doping region which contacts the second-conductivity-type well under the STI positioned between the second-conductivity-type well and the second diode diffusion region. If necessary, a semiconductor device can be fabricated with both of the aforementioned elements.
In order to accomplish the second object of the present invention, there is provided a method for fabricating a SOI semiconductor device. A surface silicon layer is formed by inserting an insulating layer on the first-conductivity-type semiconductor substrate. An etch stopper layer and oxide layer are sequentially formed on the surface silicon layer. The oxide layer and etch stopper layer are selectively etched to expose a predetermined portion of the surface silicon layer to be used for an element separating region. A trench is formed using the etched oxide layer as a mask to sequentially etch a predetermined thickness of surface silicon layer, insulating layer and semiconductor substrate. An insulating layer is sequentially formed to fill the trench and a STI formed in the trench by performing a CMP treatment such that the etch stopper layer is at a predetermined thickness. The remaining etch stopper layer is removed. A predetermined portion of the inner part of the surface silicon layer is doped by selectively ion-implanting a second-conductivity-type impurity to form a first transistor and, at the same time, form a second-conductivity-type well in the semiconductor substrate thereunder. A gate electrode is formed by forming a gate insulating layer on the surface silicon layer at the top of the second-conductivity-type well. Spacers are formed at both lateral walls of the gate electrode. First and second grooves are formed by selectively etching the surface silicon layer and insulating layer to expose the surface of the second-conductivity-type well at one side of the gate electrode and that of the semiconductor substrate, both of which are positioned apart at a predetermined distance with the STI being formed therebetween. A source/drain region is formed in the surface silicon layer at both edges of the gate electrode by selectively ion-implanting a high density of the first-conductivity-type impurity where a first transistor is formed. The bottom portion of the source/drain region contacts the insulating layer. A first diode diffusion region is formed in the second-conductivity-type well under the first groove. A second diode diffusion region is formed in the semiconductor substrate under the second groove by selectively ion-implanting a high density of the second-conductivity-type impurity into a part where a second transistor is formed.
In a first additional embodiment, after formation of the second-conductivity-type well, a first-conductivity-type impurity is selectively ion-implanted to a part, where a second transistor wilt be formed, thereby doping a predetermined portion of the surface silicon layer with the first-conductivity-type impurity and, at the same time, forming the first-conductivity-type well in the semiconductor substrate thereunder.
In a second additional embodiment, immediately after formation of the second-conductivity-type well, a field ion-implanting process is performed to form another first-conductivity-type impurity doping region which contacts the second-conductivity-type well under the STI between the second-conductivity-type well and the second diode diffusion region.
In one embodiment, after formation of the second-conductivity-type well, the first-conductivity-type well is formed according to the process described above in the first additional embodiment, and another first-conductivity-type impurity doping region is formed at a predetermined portion under the STI to contact the second-conductivity-type well according to the process described above in the second additional, embodiment.
If the SOI semiconductor device is constructed as described above, the SOI device is designed in the structure where the first and second diode diffusion regions are insulated by the STI in the semiconductor substrate. Therefore, even if the distance between the diffusion regions may be shorter in the present invention than in the prior art, an actual distance between those regions in the silicon substrate, that is, an effective distance for separation, is made larger. As a consequence, the fabricating approach of the present invention makes it possible to achieve the same operational function of the SOI semiconductor device of the present invention as the conventional one, even if the SOI device of the present invention is fabricated in an area smaller than that which has been required for the conventional one.